IC Substrate In-Plane Coefficient of Thermal Expansion (CTE) Evaluation: Testing Methods, Standards,

IC substrate in-plane coefficient of thermal expansion (CTE) evaluation is a critical reliability test that quantifies the dimensional stability of package substrates across processing and operating temperature ranges. Accurate CTE measurement in the X and Y directions helps packaging engineers minimize thermomechanical stress, prevent solder joint fatigue, and control warpage during die attachment and reflow soldering. This article provides a comprehensive technical overview of IC substrate in-plane CTE evaluation, covering sample requirements, testing items, industry-standard methods such as TMA and DIC, and practical applications in semiconductor packaging.

Technical Overview

The in-plane coefficient of thermal expansion (CTE) of an IC substrate describes how the substrate expands or contracts in the X and Y directions per degree of temperature change, typically expressed in ppm/°C. Because an IC package is a stacked structure consisting of a silicon die, die attach adhesive, package substrate, molding compound, and solder joints, any CTE mismatch between these layers generates shear and peel stresses during thermal cycling. The silicon die has a low CTE of approximately 2.6 to 3.0 ppm/°C, while the printed circuit board typically exhibits 14 to 18 ppm/°C. The IC substrate sits between these two extremes, and its in-plane CTE must be carefully engineered to balance stress distribution across the package.

In-plane CTE evaluation is essential because excessive CTE mismatch accelerates solder joint fatigue, causes interfacial delamination, induces die cracking, and contributes to package warpage during reflow at peak temperatures up to 260°C. The CTE of organic substrates is also strongly dependent on temperature relative to the glass transition temperature (Tg). Below Tg, the substrate exhibits a lower expansion rate commonly designated as alpha-1 (α1), while above Tg the expansion rate increases significantly to alpha-2 (α2). Both values must be characterized to fully understand substrate behavior throughout assembly, test, and field operation.

Common IC substrate material systems evaluated include bismaleimide triazine (BT) resin laminates, Ajinomoto build-up film (ABF) substrates, epoxy-glass fiber composites, polyimide flexible substrates, and ceramic substrates such as alumina and aluminum nitride. Typical in-plane CTE values for BT substrates range from 13 to 15 ppm/°C below Tg, while build-up layers and resin-rich regions may exhibit different values. Reinforcing glass fabric often introduces anisotropy between the X and Y directions, making directional measurement a standard requirement.

Testing Samples

BGA and FCBGA Package Substrates

Ball grid array and flip-chip ball grid array substrates represent the most frequently tested sample type. These multilayer structures combine a rigid core with build-up dielectric layers and patterned copper circuitry. Strip samples are cut from the substrate panel along the machine direction (X) and transverse direction (Y) to evaluate directional anisotropy introduced by glass fabric weave and lamination processing.

CSP, SiP, and Module Substrates

Chip-scale package, system-in-package, and embedded module substrates are evaluated to verify that thinner structures and mixed material stacks maintain target CTE values. These samples often include finished panels with solder mask, surface finish, and routed circuitry, which can influence the effective in-plane expansion behavior.

Raw Core and Build-Up Materials

Bare laminate cores, copper-clad laminates, and build-up films without circuit patterns are tested for material qualification and supplier comparison. Testing raw materials isolates the intrinsic substrate properties from the effects of circuit geometry and copper distribution.

Sample Preparation Requirements

• Specimen geometry: rectangular strips typically 3 to 6 mm wide and 6 to 10 mm long, with thickness up to 2.5 mm for thermomechanical analysis
• Directional marking: samples must be clearly labeled as X (machine direction) or Y (transverse direction)
• Edge quality: cut edges must be clean, flat, and parallel, without burrs, cracks, or delamination
• Conditioning: samples are typically pre-baked at 105°C for 1 to 2 hours and stored in a desiccator to remove absorbed moisture before testing
• Copper consideration: samples may be tested as received or after copper etching, depending on whether the evaluation targets the composite structure or the dielectric material itself
• Sample quantity: a minimum of three to five specimens per direction per lot is recommended for statistical validity

Testing Items

A complete in-plane CTE evaluation typically covers the following measured and derived parameters:

• In-plane CTE below Tg (α1) in the X direction, calculated from the linear expansion slope over a defined temperature interval below the glass transition
• In-plane CTE below Tg (α1) in the Y direction, used to assess planar anisotropy of the substrate
• In-plane CTE above Tg (α2) in both X and Y directions, reflecting post-transition expansion behavior
• Glass transition temperature (Tg) determined from the inflection point of the dimensional change curve
• Average or effective in-plane CTE across a full process temperature range, such as 25°C to 260°C, for reflow warpage simulation
• Anisotropy ratio between X and Y direction CTE values, a key indicator of glass fabric reinforcement balance
• Total expansion percentage over the tested temperature span, useful for finite element model calibration

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the most widely used method for in-plane CTE evaluation of IC substrates, performed in accordance with ASTM E831 and IPC-TM-650 method 2.4.24. A strip specimen is placed in a fused silica or quartz fixture with a low-force probe resting on the specimen surface, and dimensional change is recorded while the sample is heated at a controlled rate, typically 5°C/min or 10°C/min. A low load of 10 to 50 mN is applied to maintain probe contact without inducing creep. Testing is commonly conducted from room temperature to 250°C or 300°C under nitrogen purge to prevent oxidation. The CTE is calculated from the slope of the expansion curve over specified temperature windows, and the intersection of extrapolated slopes below and above the transition identifies Tg.

Digital Image Correlation (DIC)

Non-contact optical DIC methods measure full-field in-plane strain by tracking a high-contrast speckle pattern applied to the substrate surface during heating in a thermal chamber. DIC provides simultaneous X and Y strain maps over large specimens or entire substrate panels, capturing local CTE variations caused by copper density gradients, via arrays, and cavity regions. This method is particularly valuable for warpage studies and for validating finite element models used in package design.

Strain Gauge Method

Foil or thin-film strain gauges bonded to the substrate surface measure thermal strain directly during controlled temperature ramps. The apparent strain output, corrected for gauge self-temperature effects, is converted to CTE. This approach is useful for larger samples and for in-situ measurements during assembly processes, though gauge bonding and correction accuracy limit resolution.

Moiré Interferometry and Shadow Moiré

Laser moiré interferometry provides high-sensitivity full-field deformation measurement at the micrometer scale and is used for advanced packaging studies where local CTE gradients and thermal deformation of substrate-die assemblies must be quantified. Shadow moiré is more commonly applied to out-of-plane warpage but complements in-plane CTE data for complete thermomechanical characterization.

Typical Test Conditions

• Temperature range options: -55°C to 250°C, 25°C to 260°C, or 30°C to 300°C depending on the intended application
• Heating rate: 5°C/min preferred for accurate Tg detection; 10°C/min acceptable for routine screening
• Atmosphere: nitrogen or dry air purge to prevent moisture effects and oxidation
• Calibration: instrument calibrated with certified reference materials such as fused silica and aluminum standards traceable to national metrology institutes
• Reported results: individual and mean CTE values, expansion curves, Tg, and specimen dimensions for full traceability

Applications

In-plane CTE evaluation data directly supports multiple stages of the semiconductor packaging lifecycle:

• Material qualification: verifying that new substrate lots or alternative suppliers meet CTE specifications before release to production
• Package design and simulation: providing accurate X, Y, and Z direction CTE inputs for finite element warpage and thermomechanical stress models used to predict solder joint reliability
• Solder joint fatigue assessment: quantifying the CTE mismatch driving cyclic strain in bump and BGA joints, enabling lifetime estimation using Coffin-Manson type fatigue models
• Warpage control: tuning core thickness, build-up layer count, and copper balance to keep package coplanarity within JEDEC handling and assembly limits
• Process optimization: evaluating the effect of lamination parameters, post-cure schedules, and desiccation baking on dimensional stability
• Failure analysis: comparing CTE of failed units against control samples to identify material drift, moisture absorption, or incomplete cure as root causes of delamination or cracking
• Automotive and high-reliability qualification: demonstrating CTE stability over extended temperature cycling from -55°C to 125°C or beyond, as required by AEC-Q100 and related standards

FAQ

What is a typical in-plane CTE value for an IC substrate?

Bismaleimide triazine (BT) substrates generally exhibit an in-plane CTE of 13 to 15 ppm/°C below Tg, while build-up film layers may range from 25 to 60 ppm/°C depending on filler content. Ceramic substrates are much lower, with alumina around 6 to 7 ppm/°C and aluminum nitride near 4 to 5 ppm/°C. Acceptance limits are defined by each package design based on die size, bump pitch, and board-level requirements.

Why must CTE be measured separately in the X and Y directions?

Glass fabric weave geometry and lamination processing create anisotropy between the machine and transverse directions of the substrate panel. Unequal X and Y expansion produces asymmetric package deformation and localized stress concentration, so both directions must be characterized independently.

What is the difference between in-plane and out-of-plane CTE?

In-plane CTE refers to expansion in the X and Y directions, which is constrained by glass fabric reinforcement and remains relatively low. Out-of-plane CTE refers to thickness direction (Z) expansion, which is dominated by resin and can be several times higher, particularly above Tg. Both parameters are needed for complete substrate characterization.

What temperature range should be used for testing?

The range should reflect the actual thermal exposure of the package. For reflow compatibility studies, 25°C to 260°C covers lead-free assembly temperatures. For operational reliability, a range such as -55°C to 150°C aligned with temperature cycling profiles is appropriate. Testing through Tg is essential to capture both α1 and α2 values.

How much sample material is required for TMA testing?

Standard TMA testing requires strips of approximately 3 mm width and 6 to 10 mm length with thickness up to about 2.5 mm. Three to five specimens per direction are recommended, meaning a small coupon from the substrate panel perimeter is usually sufficient for a complete evaluation.

How does moisture affect in-plane CTE measurement results?

Absorbed moisture plasticizes the resin system, shifting the apparent Tg and altering expansion behavior. Samples should therefore be baked and stored dry before testing to ensure reproducible results, especially for moisture-sensitive build-up materials and substrates stored in ambient conditions.

Which standards govern IC substrate in-plane CTE evaluation?

Commonly referenced standards include ASTM E831 for linear thermal expansion by TMA, IPC-TM-650 method 2.4.24 for z-axis and in-plane expansion of printed boards, IPC-4101 for laminate materials, and JEDEC guidelines for package-level thermomechanical characterization and warpage measurement.